library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity conector13 is
Port ( valorMem : in STD_LOGIC_VECTOR (81 downto 0);
pl: in std_logic;

microinst: out STD_LOGIC_VECTOR (1 downto 0);
prueba: out	STD_LOGIC_VECTOR (3 downto 0);
vf: out std_logic; 
liga : out STD_LOGIC_VECTOR (11 downto 0);
EPC : out STD_LOGIC_VECTOR (2 downto 0);
PC : out STD_LOGIC_VECTOR (2 downto 0);
ERA :  out STD_LOGIC_VECTOR (2 downto 0);
RA : out STD_LOGIC_VECTOR (2 downto 0);
EY :  out STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0);
EX :  out STD_LOGIC_VECTOR (2 downto 0);
X : out STD_LOGIC_VECTOR (2 downto 0);
CBD: out std_logic; 
AS: out std_logic; 
RW : out std_logic; 
CRI : out std_logic; 
CZ : out std_logic; 
CV : out std_logic; 
CC : out std_logic; 
CN : out std_logic; 
B : out STD_LOGIC_VECTOR (8 downto 0);
HB : out std_logic; 
DUPA : out std_logic; 
OEUPA : out std_logic; 
UPA : out STD_LOGIC_VECTOR (8 downto 0);
WA : out std_logic; 
EA : out STD_LOGIC_VECTOR (1 downto 0);
WB : out std_logic; 
EB : out STD_LOGIC_VECTOR (2 downto 0);
selmux : out std_logic; 
selbus : out std_logic);

end conector13;
architecture Behavioral of conector13 is
begin
process(valorMem,pl)
begin
if(pl='0') 
	then 
	
microinst   <= valorMem(79 downto 78); 
prueba		<= valorMem(77 downto 74);  
vf 			<= valorMem(73); 
liga  		<= valorMem(72 downto 61); 
EPC			<= valorMem(60 downto 58); 
PC				<= valorMem(57 downto 55); 
ERA			<= valorMem(54 downto 52); 
RA				<= valorMem(51 downto 49); 
EY				<= valorMem(48 downto 46);     
Y				<= valorMem(45 downto 43); 
EX				<= valorMem(42 downto 40); 
X				<= valorMem(39 downto 37); 
CBD			<= valorMem(36);
AS				<= valorMem(35); 
RW				<= valorMem(34); 
CRI			<= valorMem(33);  
CZ				<= valorMem(32);  
CV				<= valorMem(31);  
CC				<= valorMem(30);  
CN				<= valorMem(29); 
B				<= valorMem(28 downto 20); 
HB				<= valorMem(19); 
DUPA  		<= valorMem(18);  
OEUPA 		<= valorMem(17);  
UPA   		<= valorMem(16 downto 8);
WA    		<= valorMem(7);  
EA    		<= valorMem(6 downto 5);
WB    		<= valorMem(4);  
EB    		<= valorMem(3 downto 2);
selmux		<= valorMem(1);
selbus		<= valorMem(0);


	
		
	elsif (pl='1') then
microinst   <= valorMem(79 downto 78); 
prueba		<= valorMem(77 downto 74);  
vf 			<= valorMem(73); 
liga			<= "ZZZZZZZZZZZZ"; 
EPC			<= valorMem(60 downto 58); 
PC				<= valorMem(57 downto 55); 
ERA			<= valorMem(54 downto 52); 
RA				<= valorMem(51 downto 49); 
EY				<= valorMem(48 downto 46);     
Y				<= valorMem(45 downto 43); 
EX				<= valorMem(42 downto 40); 
X				<= valorMem(39 downto 37); 
CBD			<= valorMem(36);
AS				<= valorMem(35); 
RW				<= valorMem(34); 
CRI			<= valorMem(33);  
CZ				<= valorMem(32);  
CV				<= valorMem(31);  
CC				<= valorMem(30);  
CN				<= valorMem(29); 
B				<= valorMem(28 downto 20); 
HB				<= valorMem(19); 
DUPA  		<= valorMem(18);  
OEUPA 		<= valorMem(17);  
UPA   		<= valorMem(16 downto 8);
WA    		<= valorMem(7);  
EA    		<= valorMem(6 downto 5);
WB    		<= valorMem(4);  
EB    		<= valorMem(3 downto 2);
selmux		<= valorMem(1);
selbus		<= valorMem(0);

end if;
end process;
end Behavioral;